RTU 2016 Question Paper Semester IV Electrical Engineering Digital Electronics

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F{ B.Tech. IV-Sem (Back) Bxam; June-July 2016
N Electrical Engineering
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\il 4EE2(O) Digital Electronics

Time: 3 Hours
Maximum Marks: 80
Min. Passing Marks (Main & Back): 26
Min. Passing Marks (Old Back): 24
I nstruction s to Candidate s : -

Attempt any five questions, selecting one question
from each unit. Att
Questions carry equal marks. schematic diagrams must be shown
wherever necessary. Any data you
feer missing suitabry be assumed and
stated clearly.
units of quantities used/ calculated must be stated crearry.
use of following supporting material is permitted
during examination.
(Mentioned in form No.205 )

UNIT.I
Q.1 (a) Convert the following into the Gray'number.
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(i) 3A7 rc
(ii) 5278
(iii) 652rc
(b) Perform the following decimal subtraction in BCD by the
9's cornplement
methods.
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(i) 30s.s - 168.8
(ii) 67s.6- 88s.9
(c) Convert 756.6038to hex.
t2)
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lt6201

OR
Q.1 (a) perform following:
(i) Multipty ilO12 by lt02 t6l
(ii) Divide I I0l0l .112by t}t2
(b) Converr 25gg.675rcto hex.
(c) Solve the following subtraction t3l
in XS _ 3 code.
(i) 267 - 17s tsl
(ii1 s7 '6 - 27.8
(d) Encode data bits 1101 into the
7 bit even
- parity hamming code. t2l
UNIT.II
Q.2 (a) Show that (A+B) an is equivalenr
to AOB. Also construct the
corresponding
logic diagrams.
(b) Reduce the expression f (B+BC) tsl
= (B+SC) (B+Dy
(c) Reduce using mapping the expression. t4)

f = X m (2. 3, 6,7, g, 10, l l, L7)
13, 14)

Q2 (a) Reduce the expression f - , ,, (ff 6,
12, 13, t4)+ d (2.4) andimplement
real minimal expression the
in universal logic.
(b) Imprement the folrowing function tl2l
using onry NoR gates.
f =a(b+cd) bc l4l

UNIT-III .

Q'3 (a) Give the definitions of voltage and
current levels corresponding
to the logic .o,
. and logic ,I, states,
as follows: _
Val (min)' Vss (min); Vs (max), Hl
Va (max),V61(max), In1, 1611,
(b) Draw and exprain the working f61
of two - input TTL (NAND)
Gate. what is totem_
pole output? Exprain its
advantages and disadvantages.
u2l

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It6201

OR
Q.3 (a) Draw and explain the working of two input ECL oR ilrloR gate.
tgl
(b) Show the circuit diagram of two - input CMOS NAND gate and describe it.
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Q.4 (a) Implement the following function using g _ to -1 MUX
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f (x. y, z) = Im (0,2,3,5)
(b) Sketch the logic diagram of 2 bit magnitude comparator and briefly explain its
operation. tgl
OR
Q.4 (a) Design the 4 input priority encoder with truth table and draw its logic
diagram. tgl
(b) Draw and explain the logic diagram of BCD adder using two 4 bit adders and a
correction detection circuit.
t8l
UNIT.V
Q.s (a) Draw and explain the operation of 4 bit bidirectional shift register.
tSl
(b) Write the complete steps of design of synchronous 3 bit down counter with truth
tables and state diagram.
l8l
OR
Q.5 (a) Convert rhe S - R flip flop to J - k flip flop.
tgl
(b) Sketch the logic diagram of a 4- bit controlled buffer register and briefly explain
irs operation.
Igl

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