RTU 2016 Question Paper Semester IV Bio Medical Engineering Digital Electronics

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F{ B.Tech. IV-Sem (Main & Back) Exam; June-July 2016
N Bio Medical Engineering
EI
s 4BM3 Digitat Electronics
BM, EX, EI, EC

Time: 3 Hours . Maximum Marks: 80
Min. Passing Marks (Main & Back): 26
Min. Passing Marks (Old Back): 24
Instructi.ons to Candidates : -

Attempt any fi,ve questions, selecting one question from each unit'
All
must be shown
Questions carry equal marks. Schematic diagrams
and
wherever necessary. Any data you feel missing suitably be assumed
stated clearlY.
Units of quantities used"/ calculated must be stated clearly.
Use of following supporting material is permitted during examination'

(Mentioned in form No.205 )

UNIT.I
l4x3 =l2l
Q.1 (a) Perform the following operations-
(i) (68)ro - (31)ro using BCD subtraction'
(ii)(1101101-1010111)2usingl,scomplementmethod.

(iiD (22 - 3t)nusing 9's complement method'
(iv) (1101101)66r+( )2.
(b) write a short note on error corection & detection codes. l4l

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OR

Q.l (a) Simplify the
t4x2=8)
(i) AB + ABC + A(B + AB)
r_
(ii) [esrc+BD)+an]c
(b) Find the value of x
t2+2 = 4l
(i) (23)* + (12)x= (l0t)x
(ii) (1000)x = (il2)3
(c) Implement Boorean funcrion f
=(w + i) (* +i + r) (y +i)using NoR gate
only.[4]

UNIT.II
Q'2 (a) what do you understand by TTL logic.
How open colector TTL is different
from
normal TTL circuit.

(b)WritedownthecomparisonbetweenCMoS&TTLfamilies.

OR
'<'/
Q'2 (a) Draw & exprain rhe working of DTL-
NAND gate.
t6l
(b) Explain the construction & operation
of M.SFET. Implement the NAND
&
NOR gate using NMos rogic circuit.
L4+6=101

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UNIT.III

Q.3 (a) Obtain & realizethe minimum SOP expression by using K map for f (A, B, C, D)

= fi M (0,2, 5,7, 8, 10) t8l

(b) Write a short note on variable mapping. t4l
(c) Develop the truth table for. t4l
f =escD +ABCD + ascP +TBaD

OR

Q.3 (a) By using Quine- McCluskey method minimize the given output function. t8l

f = Em (0, 1, 4, 7, 8, 10, 12, 13, 14) + 16 (5, 9)

(b) Aee +Aee +A ge +ABe Convert into POS form. t4)

(c) Convert f =A n+C + Rn D into canonical SOP form. t4)

Q.4 (a) Draw & explain the logic diagram of binary Adder & substractor. t8l

(b) Write a short note on Diode switching matrix. t8l

OR

Q.4 (a) Design the combinational logic circuit for BCD to EX-3 code converter. t8l
(b) Implement the following: l4x2=81

(i) Full adder using half adder only
(ii) f (A, B, C) = n M (0, 4, 6,7) using 8:1 Mu*

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UNIT.V
Q.5 (a) Draw the four bit binary ripple counter diagram using flip -flop that trigger on
the positive edge. t8l

(b) Realization of l4x2=81

(i) RS FF to JK FF
(ii) JK FF to D FF
OR

Q.5 (a) What do you understand by race around condition. How it over come in master
slave JK FF. t8l

(b) Write a short note on shift registers. t8l

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